A TRANSISTOR LEVEL ANALYSIS FOR A 8-BIT VEDIC MULTIPLIER
نویسندگان
چکیده
منابع مشابه
A High Speed and Low Power 8 Bit × 8 Bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates
The paper proposes a novel design of two transistor (2T) XOR gate and its application to design an 8 bit x 8 bit multiplier. The design explores the essence of suitably biasing the MOS transistor and engineering the threshold voltage of the MOS transistor through appropriate biasing and device geometry. Using the 2T XOR gates, a full adder has been realised. Detailed simulations have been carri...
متن کاملLow Power High Speed 16x16 bit Multiplier using Vedic Mathematics
High-speed parallel multipliers are one of the keys in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. A simple digital multiplier (henceforth ...
متن کامل32-bit Mac Unit Design Using Vedic Multiplier
This paper presents Multiply and Accumulate (MAC) unit design using Vedic Multiplier, which is based on Urdhva Tiryagbhyam Sutra. The paper emphasizes an efficient 32-bit MAC architecture along with 8-bit and 16-bit versions and results are presented in comparison with conventional architectures. The efficiency in terms of area and speed of proposed MAC unit architecture is observed through red...
متن کاملBit-Level Systolic Architecture for a Matrix-Matrix Multiplier
Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial parallel multiplier, which can perform both positive and n...
متن کاملApplication of Dynamic Pass-Transistor Logic to an 8-Bit Multiplier
Dynamic pass-transistor logic (PTL), which combines pass-transistor logic with dynamic logic, is proposed for high-performance VLSI circuit design. The dynamic PTL holds the merits of fast evaluation characteristics as dynamic logic. Moreover, because a pre-charged scheme solves the weak logic ‘high’ problem of a static PTL, an additional level restoration circuit is not needed. An 8-bit multip...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Electronics Signals and Systems
سال: 2012
ISSN: 2231-5969
DOI: 10.47893/ijess.2012.1086